1. Field of the Invention
This invention relates to the field of integrated circuitry for writing data to a magnetic medium, and more particularly, to techniques for generating a precompensation delay in the path of the write data stream.
2. Background Art
In computer systems, information is stored on magnetic storage systems such as Winchester type hard disks or floppy disks. Data is stored in a series of spiral or concentric rings known as "tracks". The data consists of streams of transitions of polarity of magnetic particles on the disk surface. A number of schemes are used to detect these transitions and data.
One prior art data detection method is a peak detection system. A disadvantage of peak detection schemes is limited data density. Another prior art data detection scheme is known as partial-response class IV (PR-IV) signaling. Systems using PR-IV schemes can achieve higher recording density than the conventional peak detection systems.
A PRML (partial response maximum likelihood) channel can be used to achieve high data density in writing and reading digital data on the disks. PRML coding assumes a linear channel. However, the recording characteristics of a magnetic medium such as a disk are nonlinear due to intersymbol interference (ISI). Nonlinear distortion in the recording process leads to degradation at higher densities and data rates. Narrow pulses in certain patterns of digital data signals experience pulse compression and other nonlinear pulse-edge displacement effects when stored magnetically on a disk file. The resulting data read back from the disk has a higher error rate because the nonlinear edge timing shifts reduce the timing margin for error of the data detection system. If the pattern-dependent edge shifts can be ascertained for the particular medium, then it is possible to preshift the write data pulse edges by an amount equal and opposite to the direction in which the medium will shift them. As a result, data with the correct timing relationships is read back from the disk. Timing precompensation decreases error rates and increases disk file capacity. Particular algorithms for determining which pulse edges to shift are well known, and are not described in detail. The amount of capacity improvement obtainable for any algorithm depends upon the accuracy of the time shifts delivered by the precompensation circuit.
The present invention relates to high-density magnetic recording of digital data, and more specifically concerns electronic circuits and methods for producing very accurate timing variations in the clocking of high-speed write data to be recorded upon magnetic media, so as to compensate for nonlinear properties of the media. It is designed for disk drives employing a method of recording termed constant density recording where the data is written in each track (or in a zone of tracks) so that the signal density is constant across all tracks in a zone. As a result, the frequency of recording of such data in outer radius tracks is higher than the frequency of recording in the inner tracks. In constant density recording the write current time period defines the recorded data length (which also varies with the track radius) so that, ideally, each pulse, when recorded, has the same length.
The prior art has employed two techniques to implement constant density recording. The first method varies the rotational speed of the disk and senses data at a constant data rate. The second technique maintains the rotational speed of the disk constant, while increasing the recording rate as tracks approach the outer edge of a disk. The first method has been used in floppy disk drives. In hard disk drives it is difficult to vary the disk rotation speed and they typically use different recording rates for different zones of tracks, depending upon the location of the track on the disk.
One conventional technique for obtaining time shifts and delays for this purpose is to use RC or other analog timing circuits. This technique is severely limited by component tolerances and environmental factors such as temperature. Another technique relies upon propagation delays of logic gates to determine time intervals of pulse edge shifts. However, logic-gate delays are inherently highly variable with environmental factors and process variations. A third method is to synchronize all signals to a compensation clock operating at a frequency high enough to allow all precompensation intervals to be specified in integral numbers of cycles of the compensation clock. A write precompensation modulation waveform of the simplest algorithm is shown in FIG. 1. The trailing edge 101 is shifted by an amount delta L, due to the interaction of neighboring bits.
One recent application is described in a paper by Philpott, Kertis, Richefta, Schmerbeck and Schulte entitled "A 7 MB/Sec (65 MHz), Mixed Signal, Magnetic Recording Channel DSP Using Partial Response Signalling with Maximum Likelihood Detection", 1993 IEEE Custom Integrated Circuits Conference, pp. 10.4.1-10.4.4. The schematic of the circuit employed in this technique is illustrated in FIGS. 2 and 3. According to FIG. 2, a combined data and clock signal 201 enters two different delay blocks 203 and 205. The first block 203, named Fixed Delay, compensates for the nonlinearities in the circuit. Precompensation delay block 205, named Variable Delay Circuit, delays the signal in time with respect to the first block 203, when the precompensation select bit 207 in a multiplexer 209 enables precompensation delay mode. The output signal 211 at node C has a delay that is the difference between the two block delays. Thus, this application requires two delay elements and requires that they are accurately matched.
Further, as seen in FIG. 3, the delay is not matched to the write current time period and is not an accurate percentage of the write current time period. According to FIG. 3, showing a detailed schematic of the Variable Delay Circuit from FIG. 2, a differential signal enters the circuit at pins MIN 301 and PIN 303, and is amplified with an NPN differential amplifier 305. Emitter-followed outputs from the differential amplifier 305 drive the capacitors 307 and 309 at pins I0 311 and I1 313. The voltage on the capacitors 307 and 309 is monitored by two Schmidt trigger circuits 315 and 317 that share common outputs 319 and 321. The variable delay is achieved by changing the discharge rate of the capacitors 307 and 309, affected by sinking a current from pins I0 311 and I1 313. This current is controlled by a 5-bit DAC, shown in FIG. 2. Only one Schmidt trigger is powered on at a time to toggle the output and the selection is accomplished by a PNP differential pair 323, connected to the input signal at nodes MIN 301 and PIN 303. The design has drawbacks and limitations which limit its effectiveness.
In prior art approaches, phase locked loops have been employed to provide for timing control. A prior approach followed by IBM has been described in several articles including Coker et al., "Implementation of PRML in a Rigid Disk Drive", IEEE Trans, on Magnetics, Vol. 27, No. 6, November 1991, pp 4538-4543; and Cideciyan et al, "A PRML System for Digital Magnetic Recording", IEEE Journal on Selected Areas in Communications, Vol. 10, No. 1, January 1992, pp 38-56. The IBM technique does not permit easy adjustment of the delay period to compensate for nonlinear distortion as the write head changes tracks on the disk nor can the technique be used with constant density recording which requires the delay period to change dynamically as a function of the bit rate.
Another prior art circuit is shown in FIG. 4. A sawtooth ramp circuit is formed by a reset transistor 401, capacitor 403 and a programmable current source 405. A programmable threshold VT 407 is set by resistor 409 and a programmable current 411. A comparator 413 is used to detect the moment when the ramp voltage VR 415 crosses VT 407. The trailing edge delay of the output signal VO 419 is varied by varying VT 407. The circuits waveforms are presented in FIG. 5. The threshold VT 407 is set to VTO 501. When a trailing edge delay of the output signal VO 419 is desired, the threshold is lowered to VTL 503. This technique is difficult to use with constant density recording (which requires the delay period to change dynamically as a function of the bit rate) since the delay element is not matched to the timing circuit. Moreover, when a large amount of delay is required, the comparator's output pulse becomes too narrow and difficult to use.